1. Field of the Invention
The present invention relates to a voltage regulating technique for logic circuits including a current switch. Particularly, the invention relates to a voltage lowering technique for bipolar transistor/MOS transistor-mixed logic circuits based on a BiCMOS process.
2. Background Art
Recent years have seen a significant increase in the processing speed of information processing equipment due to the improvements in semiconductor devices made possible by decreasing design rules. In particular, there has been a significant increase in the communication speed of information transmission based on the Internet-related optical communication networks, for example. In ICs for ultra high-speed communications, bipolar transistors and MOS transistors are mixed to meet the demand for higher speeds and lower power consumption.
An example of a BiCMOS logic circuit in which higher speeds are required is an emitter-coupled logic circuit in which a bipolar transistor is used in a current switch portion and an n-type MOS transistor is used in a constant current source. FIG. 12 shows an example of a basic circuit configuration of such a BiCMOS logic circuit. In FIG. 12, numeral 1001 designates an emitter-coupled logic circuit, and numeral 1002 designates a reference voltage generating circuit. The emitter-coupled logic circuit 1001 is made up of a current switch consisting of a pair of bipolar transistors 1011 and 1012, an n-type MOS transistor 1014 for constant current supply, and resistor means 1005 and 1006 for obtaining an output voltage.
The reference voltage generating circuit 1002 is made up of a constant current source 1017 and an n-type MOS transistor 1016 that mirrors the current flowing in the constant current source 1017 with the current flowing in the constant-current supplying n-type MOS transistor 1014. The operation of this circuit is briefly described in the following. Complementary signals are applied to input terminals 1007 and 1008. For example, when the input 1007 is at a high level and the input 1008 is at a low level, the bipolar transistor 1011 is turned on and the bipolar transistor 1012 is turned off. Thus, a current ICS flowing in the MOS transistor 1014 flows along a path consisting of the power supply 1003, resistor means 1005, and bipolar transistor 1011. As a result, an output 1009 occurs at a low level due to a voltage Va dropped by the resistor means 1005 and current ICS, while an output 1010 increases to a voltage VDD of the power supply 1003.
The product of the resistor means 1005 and the current ICS constitutes an output amplitude Va. Since the input and output signal levels are equal, a high-level input becomes VDD and a low-level input becomes VDD−Va. Since a current mirror circuit is formed by the n-type MOS transistor 1014 and n-type MOS transistor 1016, namely, their gates share a common reference voltage, the current source current ICS that flows in the n-type MOS transistor 1014 is substantially the same as the current flowing in the n-type MOS transistor 1016 (see Patent Document 1, for example).
(Patent Document 1)
JP Patent Publication (Kokai) No. 2001-267859 A